Feasibility study for a good reason
Whether we check your product specifications for feasibility or clarify the feasibility of ideas generated with you, a feasibility study is the quick and cost effective way to do so. It helps to minimize the development risk and to estimate the course of the project. Especially in this phase, you benefit from our in-depth knowledge of the SiGe BiCMOS technology of our partner IHP.
Procedure for a feasibility study
As a first step of the feasibility study, the current state of technical development is surveyed based on a literature review. After evaluating the radar front ends relevant to your project, we will make several proposals for a system architecture and evaluate them. Here the first order simulations of the most important building blocks of the system are an essential step. Through them we can ensure the possibility of implementing the entire IC and estimate performance parameters. At this stage, we develop basic test methods for important parts of the system and for the entire IC. They serve later for the verification of the specifications.
You will receive a comprehensive report containing literature research, patent research, simulation results, and suggestions for testing. Based on this broad considerations, a solid cost estimate and a schedule for the project can be created. At this point it is also possible to make a decision against the implementation of a project or to redefine a project.
Circuit design is the central activity in the development of an ASIC on chip level. At its core it is theprocess to design and optimize each chip block in several iterations.
Design and Simulation
The design of analogue circuits starts with a schematic, which is used for various time and frequency domain simulations and optimizations. Passive layout structures such as transmission lines and inductors have to be simulated using 2.5D and 3D electro-magnetic simulations. For very high frequencies even the small interconnects have to be simulated. An optimized schematic is used for the layout design, which transfers the schematic to the production technology. Once more these layouts have to be simulated and in turn may have to be optimized leading – an iterative process of schematic and layout changes till the final design.
Chip performance can be optimized for various parameters such as frequency range, output power, noise level, chip size, power consumption, temperature range. These parameters cannot be simultaneously optimized. Our goal is to find an optimal trade-off for the given application with you.
Real World Tests
Simulated and measured chip performance usually shows some difference and a redesign of the chip may be necessary. Designer experience is the crucial factor here – not just for proper design and simulation but also for foreseeing the difference between the simulated and expected measured performance. Our design team can provide this knowledge avoiding unnecessary iterations.
Typical Parameters for MMIC Optimization:
- Frequency range
- Output power
- Noise level
- Chip size
- Power consumption
- Temperature range
In the development of MMICs, the packaging of silicon chips occupies a special position. Due to the high frequencies present it affects the basic functions of the chips. There are effects due to parasitic inductances, capacitive interactions of various components, conductor resistance or the dielectric constant of the molding compound. To bring the performance of your ASIC in your application to its limits, we optimize these parameters. To reduce costs, we often resort to proven and efficient standard solutions such as QNF packages.
Not only the choice of the type of package – whether LGA, QFN or FAM and Glop Top – but also methods for connecting the chip and package such as flip chip or wire bonding or thermal management are evaluated under different aspects. For this purpose, computer-based simulations are used in the first place, but also prototyping and sample series are used here.
Our experienced network of packaging partners guarantees you access to the latest and most specialized package building processes. Every development of a package takes place in close cooperation with these partners. In this way, we can guarantee the feasibility of our designs and make the transition from pilot series to series production seamless.
- HF compliant
- Small size
- RoHS compliant
- Standard QFN layout possible
From a working sample to a series
We organize the complete supply chain for you, including forecast planning and quality assurance. You can rely on our sophisticated supply chain management. This begins with the selection and evaluation of suppliers according to criteria that meet your specific requirements. The performance of the suppliers will be monitored throughout the entire production period. If deviations from the specifications or change requests occur our corrective action management applies. As far as possible, we also provide a second source, so that even the extreme case of the failure of a supplier is hedged.
In the foundry a series can be produced starting from a batch size of 6 wafers. All subsequent production steps, such as packaging and testing, are sized as needed. Wafers that cannot be processed immediately, but also larger volumes of produced circuits, can be safely stored in accordance with current standards. We can look back on a long list of successful development projects. This experience results in the great expertise of our RF developers and a network of development partners that has grown over many years. With this innovative potential, we always put together the right team for your needs.
- Certification and qualification of partners according to ISO9001: 2015 is the minimum requirement for all partners in the supply chain
- Our products are compliant with: REACH / RoHS, Dodd-Frank-Act (EICC GeSI Common Reporting), ODC (Ozone Depletion Chemicals)
Ready for Radiation up to 300 krad
Under special conditions, RF chips are required to withstand an increased level of radiation. This can be the use in airplanes, satellites or industrial plants. We were able to demonstrate radiation resistance on various products from our development. For example, when testing an X-band PLL and an X-band transceiver, no variations of the function were found in the TID (Total Ionizing Dose) tests. And in the heavy ion test only minor SEL (Single Event Latchups) and SET (Single Event Transients) could be detected.
- Both chips produced in SiGe SGB25V technology of IHP
- Tested without packaging
- Accumulated dose up to 300 krad (Gamma ray)
- Retest after annealing 24 hrs at room temperature and 168 hrs at 100° C
- TID Tested at HZB Helmholtz Zentrum Berlin, Germany
- SEU tested at 25°C and SEL tested at 85°C
- SEE Test at Cyclotron Resource Centre at Louvain-la-Neuve / Belgium